important product information: do not discard xc18v00 prom errat a and deviatio n s from xc18v00 dat a sheet ds026 -e01 (v1.1) march 1 0 , 2004 errata notice these erra ta apply only to xc1 8 v00 pro m s. these erra ta do not a p ply to an y other p r om s. if using a differ e nt p r om, check for errata spe c ific to th at dev i ce. than k you for your interest in the enclo sed xc18v0 0 device s . althoug h xilinx has ma de ev ery effort to ensure th at these devices are of t he hi ghe st possibl e quality, these d e vi ce s a r e su bject to t he limitation s descri bed i n the followi n g errata. ple a se note tha t wh ile the s e errata will not affect m o st custo m er appli c ation s , we re comm e nd that yo u review th ese errata a nd th e deviation s from the pu b lishe d data she e ts to en sure that the e n clo s e d unit( s) me et(s) yo ur appli c atio n requi reme nts. obtaining the most recent version of this document by its very n a ture, a n e r rata noti c e i s a living do cument a nd i s su bje c t to u pdate s ba se d on re ce nt finding s. if this do cume nt is printe d or saved locally i n electroni c form, plea se che c k for the most re cent relea s e, avai lable to regi st ere d users via the xilinx www.xilinx.com/support web site. if you have addition al qu estion s afte r revie w ing t h is d o cume n t, please co ntact you r lo cal xilinx fiel d appli c atio n engin eer (fa e ) or sales re pre s entative. see: www.xilinx.com/support/ser vices/contact_i n fo.htm . devices affected by these errata these errata apply only to the followin g par t num bers with the topmark ?art? (table 1 ) . dev i ce t y pe s xc18v5 12p c20 c , xc18 v512so2 0c, xc18v51 2vq44 c , xc18v0 1 pc20c, xc1 8 v0 1so20 c , xc18v01vq 4 4 c , xc18v0 2 pc44c, xc 18 v02 v q 4 4c , xc18v04pc44c, xc18v04vq44c packag es vq44, pc44, pc20, so20 dat e co des all t able 1: de v i c es a f fe cted ds026 -e01 (v1.1) march 1 0 , 2004 www . x ilinx.com 1 1-80 0-255 -77 78
xc18v0 0 prom errata a nd dev i ations from xc18 v00 da ta sh eet 2 www . x ilinx.com ds026 -e01 (v1.1) march 1 0 , 2004 1-80 0-255 -77 7 8 how to identify an affected device these errata affect the abo ve part numb e rs with topm arki ng ?a rt? (se e exampl e s in table 2 ) and spe c ific idco de s de scribe d in ta ble 3. sample topm ark fo r the 44 -pin vqfp and plcc pa ckag es sample topm ark fo r the 20 -pin soic packag e sample topm ark fo r the 20 -pin plcc pa cka ge xc18v04 ? vq44 art 0233 5pm5a0233 xc18v01 ? j art 0233 5bm5a0233 x c 1 8 s art 0233 v 0 1 ? 5bm3a0233 t able 2: ex am p l es o f to p m arks dev i ce idco de xc18v5 1 2 0 5 0 3 3093 h xc18v0 1 0 5 0 3 4093 h xc18v0 2 0 5 0 3 5093 h xc18v0 4 0 5 0 3 6093 h t able 3: idco des a f fe cted operational guidelines 1. follow th e d a ta she e t to ensu r e that an external 4.7 k ? (or lowe r) re sist or is con n e c ted to the prom? s oe/reset# pin and the fpga?s init# pin. 2. whe n u s ing fpga done to drive prom ce #, ma ke su re th at the signal is within the sp ecification and ha s a fa st rise a nd fall time. when t he fpga do ne sig nal is use d to light an led and also d r ive the prom ce#, use an ex ternal buffe r to drive the l e d. 3. use a maste r mode fpg a cclk pin as the co nfig uration clk sou r ce inste a d of an external free- runni ng cl ock.
xc18v0 0 prom errata a nd dev i ations from xc18 v00 da ta sh eet important product information: intermittent configuration failure overview und e r certai n conditio n s, the affected p r om d e vice s w ill intermittently fail to c onfigure a xilinx fpga(s). the data i n the p r om is not affected, be ca use the ca u s e i s only related to th e imp r op er synchronization of the configur ation signals cclk, oe/reset#, and ce #. in most appli c ations, cu stome r s wil l not be affect ed by the s e e rrata. t he fo ll owin g matrix (tabl e 4 ) su mmari ze s the cu stome r ?s exposure to the phen ome non? co nditio n s that lead to an intermittent configu r at ion failure an d symptom s observed d u ri ng a failure. condition s fpg a so urced clo ck dri v i ng ccl k no pull- up on oe/r e set# (in i t#) pull-up on oe /res e t # (init# ) s y mpto ms external free- running clock dri v ing cclk led on c e # (do n e ) no l e d on ce# (do n e ) l e d o n ce # (do n e ) no l e d on ce# (do n e ) serial bit s trea m rotated bits pattern parallel bitstre a m spar ta nxl or e a r l i e r xc 4k or earlier extra 32 bits pattern spartan- ii or l a ter virtex or l a ter m i ssing 32 bit s patt ern indicat e s ex posur e t o con f ig u r at ion f a ilur e t able 4: fa ilure ex pos ure ma trix implicat io ns most cu stom ers will not b e affected by these errata, becau se the majority of all config uration appli c ation s use the fpg a ?s clo ck sou r ce to d r ive the cclk sig nal (ma s ter-serial or m a ster-parallel config uratio n mode s) a nd follow the ?op e ration al gui deline s ? (liste d above). in a very few ca se s, wh en cu stome r s a r e u s ing an e x ternal fre e -runnin g clo c k to drive the cclk sig nal (slave-se r ial or slave-pa rallel co nfiguration mode s) , there is no appli c ation work-a rou nd th at will avoid exposure to t he phe nome n on. therefor e , custom ers who a r e u s in g an extern al free-run n ing clo ck n eed to conve r t thei r ord e rin g co de to s c d0 799. thi s wil l en sure that they will no t receive aff e cted devi c e s identified in t able1, tabl e 2, and table 3. conditions leading to intermittent configuration failure this p hen om enon i s inh e rent in every device id entifi ed in ta ble 1, table 2, a nd tabl e 3. any of the followin g con d itions (or a n y combinatio n thereof ) will lead to intermittent config uration failu re : ? a slow ram p of the oe/re set# (init# ) sign al. as sp ecified i n the data sheet, a n external re sistor of 4.7k ? (or lower) i s required to qui ckly pull up the fpga init and p r om oe/reset# signal line . if the fpga init and prom oe/reset# signal line rises too slowly , then system noise might co rrupt the prom? s internal add ress cou n ters, thus ke epi ng the fpga from configu r in g prop erly. ? a staircase voltage of the ce# (done ) sign al. as spe c ified in t he fpga da ta sheet, do not excee d 12 m a sin k curren t on the fpg a do ne pin . bewa re of le d d r iving ci rcuits. using done ds026 -e01 (v1.1) march 1 0 , 2004 www . x ilinx.com 3 1-80 0-255 -77 78
xc18v0 0 prom errata a nd dev i ations from xc18 v00 da ta sh eet 4 www . x ilinx.com ds026 -e01 (v1.1) march 1 0 , 2004 1-80 0-255 -77 7 8 to drive the led an d the prom ce# pin di rectly (unbuffered ) e x ceed s thi s specifi c ation. thi s also affe cts the fpga driv edo n e optio n. ? whe n the fpga v cc po wers up afte r the prom v cc , the ce#-done and oe/reset#-init sign als may tran sition sl owly (while the fpga is powering u p and before the s e sign als a r e p u lled low by the fpga). ? a configuration desi gn that ut ilizes a free-running clock. slow ramp of the oe/ r eset# (init#) signal a pull-up re si stor i s re quired to pro perl y propa gate this si gnal th rough the p r om (fig ure 1). figu re 2 s h ows a c l ean oe/reset# (init#) s i gn al. however, a s l ow ramp c ould potentially allow s ystem noise to prop agate through the prom?s inp u t buffer (figu r e 3), thus cre a ting sho r t re set pulse s that might cau s e the intern al ci rcuit s to get out of sync. the ob se rve d failure rate rang es from 1% to 5% of config uratio n cy cle s . o e /r es et # ( i nit ) w i th pullup vc c 4. 7k f i gure 2: oe/reset # ( i nit # ) w i th p u ll-up resistor in fpg a init cc l k prom f i gure 1: 4.7k ? pull-u p re q u ire d f i gure 3: oe/reset # ( i nit # ) w i thout pull-up resistor recomme nd ation: follow the d a ta she e t to ensure that a n external 4. 7k ? (or lo we r) re si stor i s con n e c ted to the prom?s oe/reset# pin and the f p ga?s init pin. ensure that the fpga t icck specifi c ation is m e t (500n s). this trans lates to a t rise and t fall time of 500 ns for the prom? s oe/reset# signal . f i gure 4: rec o mmend ed res i stor value oe / r es e t # ou t ccl k vcc 4. 7 k oe/ r es et# (i ni t ) w / o pull u p 4.7k ? (o r l o w e r) fpga init pr om oe / r ese t
xc18v0 0 prom errata a nd dev i ations from xc18 v00 da ta sh eet staircas e voltage of the ce# (do n e) signal the fp ga h a s a sin k cu rrent spe c ificati on of 12 ma that is exce e ded wh en an unb uffere d l e d i s tied to the ce# (do n e) signal (f igure 5). in this sce na rio, the ce# (done) sign al is held at an intermedi ate voltage level that mimic s multiple input puls es (f igure 7). these puls e s pro pagate through the prom and cau s e the i n ternal circuits to get out o f sync. the observed fail ure rate is u p to 5 0 % of config uratio n cycle s . figu re 6 sho w s a clean ce# (done) sign al whe n it is not tied to an led. ce # w/ o l e d f i gure 6: ce# (done) w i t h out led f i gure 5: un bu ffered led f i gure 7: ce# ( d one) w i t h an unbuffere d le d recomme nd ation: whe n u s in g fpga done to drive prom ce# (to redu ce sta n d b y po wer), m a ke sure that the sign al is within th e sp ecification an d ha s a fa st rise and fall ti me. use an e x ternal buffer to d r ive any led (fig ure 8). if done is not used to drive ce#, it can b e co nne cted to an le d (fig ure 9 ) . f i gure 8 : (led w i t h buffer circuit) f i gure 9 : (unbuffered led) in fpga init done ccl k p vcc r o m ce # t # out ccl k 100 ce # wi t h l e d 100 oe/rese do ne fpga b u ffe r 330 ? ce# prom 330 ? vcco vcc o led do ne fpga led 330 ? ce# prom vcco ds026 -e01 (v1.1) march 1 0 , 2004 www . x ilinx.com 5 1-80 0-255 -77 78
xc18v0 0 prom errata a nd dev i ations from xc18 v00 da ta sh eet 6 www . x ilinx.com ds026 -e01 (v1.1) march 1 0 , 2004 1-80 0-255 -77 7 8 when the fp ga v cc powers up after the prom v cc recomme nd ations : 1. if the fpga can not be po wered up b e fore the pr o m , ensu r e th at the init signal tran sitio n s lo w before the done sig nal durin g fpga powe r-u p. o ne way to accompli sh t h is is to use a lower- resi stan ce pu ll-up on do ne and a hig her-re si stan ce pull - up on init. for example, tie th e do ne sign al to a 33 0 ? pull-u p re sisto r and ini t to a 3.3k ? pull-u p re si st or. 2. another alternative is to di sconn ect the fpga do ne sign al fr o m t he prom ce#, and con n e ct ce# to gro und. t o prevent con t ention o n the co nfiguration data lin e(s) whe n the p r om ce # i s conne cted to groun d, ei ther th e fpg a de sign mu st d r ive th e f p ga init# consta ntly lo w (therefore driving th e prom oe/reset# low), or the fpga des ign mus t not us e the fpga c onfiguration data pins (di n or d[0 - 7]) tha t are co nne cted to the prom. configuration system that utiliz es a free-running clock in most a ppli c ation s , the f p ga sou r ce s the cclk signal, which synchroni ze s wi th the ce# (done) and oe/reset# (init#) s i gnals . however, in an as ync h ronous s y s t em (figure 10), meaning when an external fre e -runni ng cl ock drives t he configuration clo ck si gn al (cclk), the r e is a po ssi bility that a missed o r extra pul se (o r p u lse s ) ca n be interp reted b y the prom? s internal cou n ters as ccl k transitio n s while the oe /reset# (init#) s i gnal is in its interm ediate phas e (figure 11). t he obs e rved failure rate rang es from 0.1% to 1% of configuratio n cycle s . ce # ccl k oe/rese t # in fpga init done ccl k prom ce # oe/r ese t# out ccl k f r ee run n ing clo c k f i gure 1 0 : as ynchro nous s y s t em f i gure 1 1 : ccl k and oe/reset # collisio n recomme nd ation: there is no appli c ation work-a rou nd th at will avoi d exposure to the ph enom e non whe n a free runni ng clo ck i s used . therefore, cu stome r s who a r e u s in g an external free-ru n n ing cl ock ne ed to conve r t thei r ordering code to scd0799; this will ensure that they will not rece i v e affected devices identified in t able1, table 2, and table 3.
xc18v0 0 prom errata a nd dev i ations from xc18 v00 da ta sh eet explanation of sy mpto ms and root cause rot a te d bit patte rn a rotated bit pattern occurs whe n the bit co unter a nd t he div8 circuit (figu r e 12) b e come s desynchroni zed. data bits within a byte will be consistently rotated, byte by byte (figure 13). tabl e 4 (above ) sum m ari z e s the condition s whe r e a rotate bi t pattern can occur. 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 s t ore d b i tstream 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 r o ta ted b i t bi tst r e a m out p u t ab ov e d i ag r a m s h ow s ex am pl e o f c i r c uits be i n g 4 bits out o f sy nc 32-bit by n flas h core 3 2 - b i t l a t c h address counter bit counter ser i al o u t pa rall el ou t div8 cc lk s/ p f i gure 1 2 : counte r circ uits f i gure 1 3 : example of rotat e d bit pattern extra 32 bits patter n the address cou n ter misses the first in cre m ent and repe ats the first 32 bits. table 4 (above ) summ ari z e s the con d ition s wh ere a n extra 32 bits pattern can occur. 32-bit by n flas h core 3 2 - b i t l a t c h address counter bit counter ser i al o u t pa rall el ou t div8 cc lk s/ p stored bitstrea m addr 0 32 -bits addr 1 32 -bits addr 2 32 -bits addr 0 32 -bits addr 1 32 -bits addr 2 32 -bits addr 0 32 -bits ex tra 32 bits bitstream output f i gure 1 4 : cou n ter circuits f i gure 1 5 : exa m ple of an e x tr a 32 bits patte rn ds026 -e01 (v1.1) march 1 0 , 2004 www . x ilinx.com 7 1-80 0-255 -77 78
xc18v0 0 prom errata a nd dev i ations from xc18 v00 da ta sh eet 8 www . x ilinx.com ds026 -e01 (v1.1) march 1 0 , 2004 1-80 0-255 -77 7 8 m i ssing 32 bits pattern the address counte r increme n ts mo re than once and misse s the seco nd 32 bits. table 4 (ab o ve) summ ari z e s the co ndition s where a missing 3 2 bits pattern can occur. 32-bit by n flas h core 3 2 - b i t l a t c h address counter bit counter ser i al o u t pa rall el ou t div8 cc lk s/ p stored bitstrea m addr 0 32 -bits addr 1 32 -bits addr 2 3 2 -bits addr 0 32 -bits addr 2 32 -bits missin g 32 bi ts bitstre a m out p ut f i gure 1 6 : counte r circ uits f i gure 1 7 : ex ample of a mis s ing 3 2 bits pa tte rn design fixes as discu s sed above, most custo m ers will not be affe cted by the s e errata. un a ffected custo m ers, those who use the fpga?s clo c k sou r ce to d r i v e the cclk sign al (m aste r-se r ial & ma st er-parallel config uratio n mode s) an d f o llow the ?o p e ration al gui deline s ,? sho u ld contin ue usin g the current devices. ho wever, for those fe w custome r s wh o are affecte d by these er rata, seve ral fixes for t he ro ot ca use are bein g implemented. table 5 summari zes th ese fixes. production devices fr om the new mask revision will b e available by t he middle of calendar year 2004, at whi c h time xilinx w ill i s sue a pcn to detail the changes and ho w affe cted custo m e r s can o r de r the ne w mask revision d e vice s. fixes a d d h y st eresi s to oe/res et# a nd ce # input buffers re-s y n c h roniz e bit and b y t e (di v 8 ) cou nter s at ea ch by te i n cr e m en t s y nchro n ize in tern al reset to configu ration clo ck suppres s re-i nitiati on of internal reset/ p re-lo a d w h ile a reset/ p re-lo a d is in progres s rota te d bi ts p a tte rn e x tra 32 bi ts p a tte rn sympto ms mi s s i ng 32 bi ts p a tte rn slo w r a mp oe/r eset # ( i n i t#) st airca se volt age of ce # (done ) condition s ext e rnal free running clock t able 5: summa r y of des i gn fix e s
xc18v0 0 prom errata a nd dev i ations from xc18 v00 da ta sh eet additional questions or clarificatio n s if additional q uestio n s ari s e or cla r ifications are ne ed ed rega rdin g these errata, plea se conta c t your l o cal xilinx field applicatio n engi neer (fae) o r sal e s rep r e s entative. fo r the pho ne numbe r in yo ur area, see www.xilinx.com/s upport/services/ contact _ info.htm . any feedback with rega rd t o these e r rata can b e e-m a iled to qa_com@xilinx.com . ds026 -e01 (v1.1) march 1 0 , 2004 www . x ilinx.com 9 1-80 0-255 -77 78
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